Home     Exhibits     Wanted     Articles     Advertising   +Links  

Tech Notes: Wang 700-Series Microcode Documentation
Updated 11/24/2006


The information contained in this document is developed partly from technical information published by Wang Laboratories, as well as through reverse-engineering and observation of circuit operation by the author. This information should not be considered authoritative, as some of the data is arrived at by experimental or inferred means. The author and/or the Old Calculator Web Museum assume absolutely no responsibility for any use or misuse of this information, and assumes absolutely no liability for damage, injury, or any other circumstance related to application of this information.
Please note that the Wang 700-series calculators utilize electrical potentials which can cause serious injury or death.

INTRODUCTION

The Wang 700-series calculators all utilize a unique ferrite transformer wire-rope ROM. These ROMs consist of an array of 43 ferrite core transformers, whose primary windings are made up of myriad wires wrapped (or not) around one core of the transformer. Wires that wrap around the core represent a '1', and if a wire doesn't wrap around, a '0' is represented. The ROM contains literally thousands of wires, each of which encodes one 'word' of microcode instruction. The microcode instruction is 43-bits wide, and consists of groupings of bits (fields) which define the low-level operation of the calculator. All 43 bits are accessed from the ROM once per machine cycle (near the beginning of the cycle), and are copied into a series of flip-flops configured as latches. From this point, logic networks implement the various functions of the groupings of microcode bits.

The microcode address is selected by an eleven bit address (for a total microcode size of 2048 microcode words). Each microcode instruction contains fields that indicate the address of the next microcode instruction. Nine of the eleven bits of the "next microinstruction address" are defined by the microcode instruction itself, and the remaining two bits of the "next microinstruction address" are conditional, based on the status of various machine state flip flops, allowing different branches of microcode to be executed depending on the state of the calculator. (See the JAD, JH, and JL microcode field descriptions for more information).

The 700-series calculators have a master clock frequency of 8.0 MHz, which is split up by a simple ring counter into a microcode cycle that consists of ten equally-timed non-overlapping phases, P0 through P9, with a total microcycle time of 1.25 microseconds. These phases coordinate the stepping of the logic of the microcode engine through the execution of each microinstruction.

The Arithmetic Logic Unit (ALU) of the 700-Series calculators is a four-bit parallel device. Two four-bit busses called the A and B bus serve as inputs to the ALU. Each of the A and B busses can carry data selected from various internal registers of the calculator based on the AI and BI microcode fields. The output of the ALU is the four-bit Z bus. The ALU also generates a few status conditions, such as keeping track of carries, and generating a status output that indicates if the ALU output is zero (0000). The ALU provides for logical operations on the A and B bus inputs, as well as mathematical addition (in either Binary or Binary Coded Decimal number systems as directed by the Bd microcode field), and is primarily directed in its operation by the AOP microcode field.

The random access memory subsystem of the 700-series calculators is based on magnetic core memory. The memory is accessed eight bits at a time. The model 700A and 700B contain 8192 bits of memory, organized as 1024 words of eight bits each. The model 720A, 720B, and 720C calculators contain 16,384 bits, organized as 2048 words of eight bits each. The memory is addressed by a trio of 4-bit registers designated L, M, and N, grouped together as the Memory Address Register. The Memory Address Register is loaded before a core memory cycle begins with the content of another group of three 4-bit registers designated as T, U, and V. The T, U and V registers can be loaded with the output of the ALU via microcode instructions, and their content can be directed into the ALU via the A-bus. By this means, core memory addressing calculations can be performed by using the capabilities of the ALU. The operation and addressing of the core memory subsystem is controlled by the MOP field of the microcode instruction. Memory read cycles place the memory data read out of the addressed memory location into two 4-bit buffer registers designated RA and RB. Memory write cycles place the current content of the ALU output (Z-bus) into the upper or lower 4-bits of the selected memory location as directed by the particular MOP microcode field.


WANG 700-SERIES CALCULATOR BLOCK DIAGRAM



MICROCODE INSTRUCTION FIELD DEFINITIONS

Field Name: AI
Bits: 3 (Bits 1-3)
Function: Selects A-Bus Input to ALU

The AI field selects which of eight different data sources are gated onto the 4-bit "A" bus during this machine cycle. The data sources are various working registers of the calculator. The A-Bus is one of the four-bit busses that supplies data to the Arithmetic/Logic Unit of the calculator.

AI3 AI2 AI1 Selects
0 0 0 S(Machine Status) Register
0 0 1 T Register
0 1 0 U Register
0 1 1 V Register
1 0 0 KA Register
1 0 1 KB Register
1 1 0 CA Register
1 1 1 CB Register

Field Name: BI
Bits: 3 (Bits 4-6)
Function: Selects B-Bus Input to ALU

The BI field selects which of six different data sources are gated onto the 4-bit "B" bus during this machine cycle. The data sources are various working registers of the calculator. The B-Bus is the other four-bit bus that supplies data to the Arithmetic/Logic Unit of the calculator.

BI3 BI2 BI1 Selects
0 0 0 Undefined
0 0 1 KK Field of Microcode Word
0 1 0 D Register
0 1 1 Undefined
1 0 0 KA Register
1 0 1 KB Register
1 1 0 CA Register
1 1 1 CB Register

Field Name: ZO
Bits: 3 (Bits 7-9)
Function: Selects Routing of Z-Bus output of ALU

The ZO field selects which of eight different data destinations the output of the Arithmetic/Logic Unit is directed to during this machine cycle. The Z-Bus contains the output of the ALU, and provides a parallel path simultaneously to both the core memory system, as well as to the selected machine register. The data on the Z-bus can be written into a selected core memory location (depending on the MOP microcode field), as well as gated into one of the eight selected working registers at the same time.

ZO3 ZO2 ZO1 Selects
0 0 0 S Register
0 0 1 T Register
0 1 0 U Register
0 1 1 V Register
1 0 0 KA Register
1 0 1 KB Register
1 1 0 CA Register
1 1 1 CB Register

Field Name: AOP
Bits: 3 (Bits 10-12)
Function: Selects the arithmetic/logic function of the ALU

This field selects one of eight different arithmetic or logical operations to be performed by the Arithmetic/Logic Unit during this machine cycle. The ALU takes its input from the data sources on the A and B busses selected by the "AI" and "BI" microcode fields, performs any preprocessing on the A and B bus data as directed by the AC and BC microcode fields, performs the selected operation (if addition, using number system selected by the Bd microcode field), and directs the result to the destination selected by the "ZO" microcode field.

AOP3 AOP2 AOP1 ALU Function
0 0 0 A + B -> Z (Add)
0 0 1 A + B + 1 -> Z (Add and Increment)
0 1 0 A + B -> Z, Save Carry
0 1 1 A + B + Carry -> Z, Save Carry
1 0 0 A + B + 1 -> Z, Save Carry
1 0 1 Logical "AND" of A & B Inputs
1 1 0 Logical Exclusive-OR of A & B Inputs
1 1 1 Logical Exclusive-OR of A & B, Shift Result Right One Bit, Lost bit -> Carry

Field Name: AC
Bits: 1 (Bit 13)
Function: A-Bus ALU Override

The AC bit enables the content of the A-Bus to pass into the ALU. If the AC bit is set, the A-Bus content is gated into the ALU. If it is not set, then the A-bus content is ignored, with the ALU seeing "0000" as it's A-Bus input.

Field Name: BC
Bits: 2 (Bits 14-15)
Function: B-Bus ALU Override

The BC bits determine preprocessing of the data on tbe B-Bus before it enters the ALU. The content of the B-Bus can be passed through, complimented, or forced to "1111" or "0000".

BC2 BC1 Function
0 0 Forced to "0000"
0 1 Pass Through
1 0 Forced to "1111" or "1001", based on Bd microcode field
1 1 Compliment (2's or 9's, based on Bd microcode field)

Field Name: Bd
Bits: 1 (Bit 16)
Function: ALU Math Mode

This bit selects whether the ALU operates using Binary or Binary-Coded-Decimal math. If this bit is 0, the ALU operates on Binary numbers. If this bit is 1, the ALU operates on Binary-Coded Decimal numbers.

Field Name: MOP
Bits: 4 (Bits 17-20)
Function: Memory Operation & Misc. Control

This field selects one of fifteen different memory addressing, read/write, as well as miscellaneous peripheral control operations that are to occur during this machine cycle. Memory operations (read and write) are carried out on the address currently contained in the L, M, and N registers (with the L register (most significant) containing 2 bits, and the M & N registers containing 4 bits of address, for a total of 10-bits of core memory addressing capability). Memory data is transferred byte (8-bits) at a time and is buffered in the RA(high nybble) and RB(low nybble) registers. Reading the content of a memory location is destructive, meaning that the memory location must have its content re-written by a successive microcode cycle if it is to be preserved after reading. One MOP operation code (1110) has an undocumented function. The Wang documentation that is known to exist states that this MOP function is a "spare or illegal setting", however, the schematics indicate that this function is decoded by the microcode decoding logic, and the signal generated by this decoding is used on one of the circuit boards that relates to input/output functions. The logic circuitry related to the operation of this particular MOP code is convoluted, and as yet, its functionality has yet to be determined. It is known, from dumping of Wang 700-Series ROM contents, that this MOP code is indeed used in the microcode of these machines. Harold Koplow (designer of most of the 700-Series microcode), made mention to me of the mysterious use of an "undefined" mirocode combination in the coding, but never explained it. Unfortunately, with his passing, this information is lost until it can either be decoded from the schematics, or if someone else out there may have known about it. Please, if anyone out there knows what MOP14 (1110) does, please get in touch with me via EMail.

MOP4 MOP3 MOP2 MOP1 Mnemonic Function
0 0 0 0 wra Transfer content of Z-Bus (ALU Output) to RA, then Exclusive OR content of RA & RB with byte of memory addressed by L, M, and N registers.
0 0 0 1 wrb Transfer content of Z-Bus (ALU Output) to RB, then Exclusive OR content of RA & RB with byte of memory addressed by L, M, and N registers.
0 0 1 0 rdt Transfer content of T, U, and V registers into L, M, and N (Memory Address) registers; read memory byte at location defined by L, M, and N registers into RA and RB; copy RA and RB registers to CA and CB registers. Readout is destructive.
0 0 1 1 clt Transfer content of T, U, and V registers into L, M, and N (Memory Address) registers; read memory byte at location defined by L, M, and N registers into RA and RB. Readout is destructive.
0 1 0 0 rdv Jam memory address register L to all 1's (11); transfer content of microcode field KK to memory address register M; transfer content of register V to memory address register N, read content of memory addressed by L, M and N registers into RA and RB registers, then copy RA and RB registers to CA and CB registers. Readout is destructive.
0 1 0 1 clv Jam memory address register L to all 1's (11); transfer content of microcode field KK to memory address register M; transfer content of register V to memory address register N, read content of memory addressed by L, M and N registers into RA and RB registers. Readout is destructive.
0 1 1 0 gin External Peripheral Input Function
0 1 1 1 gout External Peripheral Output Function
1 0 0 0 nop No Operation
1 0 0 1 setq Toggle Q State Flip Flop
1 0 1 0 tin Copy cassette tape data read flip-flop to least significant bit of KB register.
1 0 1 1 tout Set cassette tape data out flip-flop.
1 1 0 0 mton Turn on the cassette tape drive motor
1 1 0 1 mtoff Turn off the cassette tape drive motor
1 1 1 0 N/A ?Mystery?
1 1 1 1 N/A Undefined

Field Name: KK
Bits: 4 (Bits 21-24)
Function: Constant Field

The KK field defines a 4-bit constant value (0000 through 1111) that can be directed to the B-Bus input of the ALU if the BI microcode field is "001" (See BI description above), or can be directed to the middle address nybble (M register) of the core memory address if the MOP microcode field is "0100"(rdv) or "0101"(clv) (See MOP description above).

Field Name: ST
Bits: 4 (Bits 25-28)
Function: Status Control

This microcode field relates to the manipulation of the hardware status of the machine, including setting or clearing one of four status flip flops (S0 through S3); conditionally setting one of two of the the status flip flops (S0 and S1) depending on if the ALU Z-bus output is zero; as well as performing miscellaneous operations including enabling the keyboard for input, and setting the overflow condition.

ST4 ST3 ST2 ST1 Function
0 0 0 0 No Status Operation
0 0 0 1 Set Status Flip Flop S0
0 0 1 0 Set Status Flip Flop S1
0 0 1 1 Set Status Flip Flop S2
0 1 0 0 Set Status Flip Flop S3
0 1 0 1 Clear Status Flip Flop S0
0 1 1 0 Clear Status Flip Flop S1
0 1 1 1 Clear Status Flip Flop S2
1 0 0 0 Clear Status Flip Flop S3
1 0 0 1 Clear the Keyboard Status Flip Flop
1 0 1 0 Set Status Flip Flop S0 if Z-Bus # 0
1 0 1 1 Set Status Flip Flop S1 if Z-Bus = 0
1 1 0 0 Set Overflow Status Flip Flop
1 1 0 1 Clear Status Flip Flops S0 through S3
1 1 1 0 Set Parity Error Flip Flop
1 1 1 1 Undefined

Field Name: JAD
Bits: 9 (Bits 29-37)
Function: Fixed Portion of Next Microcode Instruction Address

The JAD microcode field defines the upper 9 bits of the address of the microcode instruction to be executed next. Microcode addresses are 11 bits in lengh, with the JAD field comprising the upper 9 bits, e.g., JJJJJJJJJHL, with "J" representing the 9 bits of this JAD microcode field, and "H" and "L" representing the low order two bits which are defined by the JH and JL microcode fields. (See JH and JL microcode fields for more information).


Field Name: JH
Bits: 3 (Bits 38-40)
Function: Part I of Conditional Next Microcode Instruction Address

The JH microcode field defines the next to the least-siginificant address bit of the microcode instruction to be executed next. The JH field selects one of 7 different conditional evaluations to be performed based on the various hardware status flip flops (see table below). The resulting bit of the next microcode address is set to 1 if the selected status flip-flop is set, or to 0 if the status flip flop is clear. Microcode addresses are 11 bits in lengh, with the result of the conditional test defining the next to the least-significant address bit, e.g., JJJJJJJJJHL, where "J" represents the bits of the JAD microcode field, "H" represents the result of the JH conditional selection, and L represents the result of the JL conditional selection (see JL description for more information).

JH3 JH2 JH1 Conditional Evaluation
0 0 0 Force H Microcode Address Bit to 0
0 0 1 Force H Microcode Address Bit to 1
0 1 0 Set H Microcode Address Bit if Status Flip Flop S1 is Set, else Clear it
0 1 1 Set H Microcode Address Bit if Status Flip Flop S3 is Set, else Clear it
1 0 0 Set H Microcode Address Bit if Overflow Status Flip Flop is Set, else Clear it. Then Clear Overflow Status Flip Flop.
1 0 1 Set H Microcode Address Bit if Carry Status Flip Flop is Set, else Clear it
1 1 0 Set H Microcode Address Bit if Keyboard Status Flip Flop is Set, else Clear it
1 1 1 Undefined

Field Name: JL
Bits: 3 (Bits 41-43)
Function: Part II of Conditional Next Microcode Instruction Address

The JL microcode field defines the least-siginificant address bit of the microcode instruction to be executed next. The JL field selects one of 7 different conditional evaluations to be performed based on the various hardware status flip flops (see table below). The resulting bit of the next microcode address is set to 1 if the selected status flip-flop is set, or to 0 if the status flip flop is clear. Microcode addresses are 11 bits in lengh, with the result of the conditional test defining the next to the least-significant address bit, e.g., JJJJJJJJJHL, where "J" represents the bits of the JAD microcode field, "H" represents the result of the JH conditional selection (See the JH description above), and L represents the result of the JL conditional selection.

JL3 JL2 JL1 Conditional Evaluation
0 0 0 Force L Microcode Address Bit to 0
0 0 1 Force L Microcode Address Bit to 1
0 1 0 Set L Microcode Address Bit if Status Flip Flop S0 is Set, else Clear it
0 1 1 Set L Microcode Address Bit if Status Flip Flop S2 is Set, else Clear it
1 0 0 Set H Microcode Address Bit if Z-Bus (ALU Output) is zero (0000), else Clear it
1 0 1 Set H Microcode Address Bit if the Q Status Flip Flop is Set, else Clear it
1 1 0 Set H Microcode Address Bit if the Saved Carry Status Flip Flop is Set, else Clear it
1 1 1 Undefined

Copyright ©1997-2011, Rick Bensene